What is another name for the translation lookaside buffer?
- address translation cache
- memory management unit
- hardware cache
Section 3.5 Translation Lookaside Buffers
In this section we discuss how to speed up the paging process. Start from Paging: Faster Lookups (TLBs) chapter, intro and sections 19.1, 19.2.
Practice 3.5.1.
Practice 3.5.2.
Practice 3.5.3.
Read section 19.3, about who handles the TLB misses.
Practice 3.5.4.
True.
False.
True or False: A TLB miss must always be handled by some appropriate software code.
Practice 3.5.5.
True.
False.
True or False: When a TLB miss is handled by the software via a trap handler, then the return from that trap handler works as "normal", i.e. it returns to execute the instruction after the one that caused the interrupt.
Read section 19.4, which discusses what is contained in a TLB entry. Make sure you also read the aside about "TLB valid bit vs page table valid bit"
Practice 3.5.6.
How does the hardware look for a possible entry in the TLB?
- It goes through each row one at a time checking for a matching VPN.
- The buffer is indexed by the VPNs, and the hardware jumps to the correct row right away.
- It checks all rows at the same time, in search of a match.
Read section 19.5 about what happens during a context switch.
Practice 3.5.7.
Which of these are valid approaches to handling the problems occurring during a context switch?
- Completely flush the TLB on each context switch.
- Add information on each row connecting the row to the address space it comes from.
- Use read/write/execute bits in the cache rows.
Read sections 19.6-19.8
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